30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Xing Wang, Yimin Du, Tianhui Jiao, Defa Wu, Xi Chen, Miaoyu Tang, Yi Yang, Zhichao Liu, An Guo, Gaoming Fu, Peng Li, Jun Dong
+8 more Bo Liu, Xinning Liu, Weiwei Shan, Hao Cai, Guangyu Sun, Lin Tong, Jun Yang, Xin Si
DOI: 10.1109/isscc49663.2026.11409034
Cited by: 1
References: 6

Abstract

Conventional FP-CIMs suffer from fixed preserved bit-width (PBW), limiting their adaptability and efficiency. This work proposes the first MXFP-CIM macro enabling wide-range adaptive PBW, featuring: (1) A serial dual-bit-sliding scheme; (2) A harmless data mapping scheme with a hierarchical hidden-bit decoder; (3) An adjustable-PBW MXFP-MAC circuit via twin-stage allocation. The 28nm MXFP-CIM macro achieves a peak energy efficiency of 127.54TFLOPS/W in the MXFP6/6 mode.

Fields of Study & Subjects

Parallel Computing and Optimization Techniques Ferroelectric and Negative Capacitance Devices Semiconductor materials and devices

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
512–514
Publication date
15 February 2026