25.3 A 16nm 0.042mm 2 0.66μJ/Ops Lightweight MLWE PQC KEM with Cryptanalysis-ASIC Co-Optimization

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Archisman Ghosh, Ming-Che Li, Lingke Ding, Suparna Kundu, Abdullah Sayeed, Angshuman Karmakar, Harshit Naman, Sarthak Antal, Ingrid Verbauwhede, Shreyas Sen
DOI: 10.1109/isscc49663.2026.11409037
Cited by: 1
References: 8

Abstract

Resource-limited devices demand post-quantum cryptography (PQC) within stringent power, area, and memory limits. To our knowledge this work introduces the first cryptanalysis-ASIC co-optimized PQC IC, achieving minimal area, power, and memory footprint. This approach achieves an area reduction of$8 \times$relative to the state-of-the-art M-LWE accelerator and up to 509× compared to a generic PQC processor. Fabricated in Intel16, this IC operates over a frequency range of 0.1 MHz to 1.03 GHz and achieves an$8.5 \times$reduction in energy-area product.

Fields of Study & Subjects

Semiconductor Quantum Structures and Devices GaN-based semiconductor devices and materials Advancements in Photolithography Techniques

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
428–430
Publication date
15 February 2026
Language
EN