A -102.2dB THD+N, 92% Efficiency, 1.08mW Idle Power Digital-Input Class-D Amplifier with Power-Adaptive Techniques and Dual-Edge Pulse-Width Adjustment Modulator
Abstract
This paper presents a digital-input Class-D headphone amplifier that achieves low noise and low idle power simultaneously. Three key techniques enable this: a power-adaptive 3 -level IDAC that scales power with signal level, an assistant IDAC that relaxes the first integrator's power consumption, and a dual-edge PWA modulator that minimizes loop filter swing. Fabricated in$0.18 \mu \mathrm{m}$CMOS, it achieves 117.8 dB DR, -102.2 dB THD+N, 0.6 mA idle current, and 92% peak efficiency when driving a 16Ω load.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Advanced Power Amplifier Design
Advanced DC-DC Converters
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 78–80
- Publication date
- 15 February 2026
- Language
- EN