A 112Gb/s PAM-4 SBD Transceiver with Mismatch-Compensated 2×VDD Hybrid and Two-Step Echo Canceller in 28nm CMOS
Abstract
A$112 \text{Gb} / \mathrm{s}$PAM-4 simultaneous bidirectional (SBD) transceiver in 28 nm CMOS is presented. It features a hybrid with a$2 \times$VDD stacked driver to restore signal swing, a joint delay and slew-rate matching scheme to eliminate dynamic glitches, and a two-step echo canceller to mitigate reflections. The transceiver achieves BER$
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Pages
- 146–148
- Publication date
- 15 February 2026