A 16Gb/s/pin 0.51pJ/b Single-Ended NRZ Transceiver with Distributed Dual-Loop V DDQ -Ripple Compensation and Dynamic Clock Duty-Cycle Calibration for Memory Interfaces
Abstract
A 16Gb/s/pin 0.51pJ/b single-ended NRZ transceiver with distributed dual-loop compensation (DDLC) for$\mathrm{V}_{\text{DDO }}$-ripple suppression and dynamic duty-cycle calibration (DDCC) for robust clocking is presented. The DDLC locally regulates$\mathrm{V}_{\text{DDQ}}$with a shared low-power LDO, reducing the required decoupling capacitor by 91.4%, while improving horizontal and vertical eye margins by 61% and 36%. Demonstrated on five channels, the proposed DDLC scales naturally to larger DQ counts for high-density memories.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Low-power high-performance VLSI design
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 632–634
- Publication date
- 15 February 2026
- Language
- EN