36.1 ReFIND: A Resolution-Reconfigurable Bio-Signal Classification SoC Enabling $>10\times$ Savings in AFE Power Per Channel
Abstract
This work presents ReFIND, an SoC integrating together 16 resolution-reconfigurable AFEs, a feature extractor, and a classifier. The VCO ADC architecture trades power for resolution by scaling the integration time, from 13 to 10 b at 1.77 to$0.12 \mu \mathrm{W} /$channel. End-to-end validation shows up to$14 \times$power saving over a fixed array,$3 \times$more than channel selection. ReFIND enables runtime resolution scaling, opening up power-performance optimization in bio-signal classifiers.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Low-power high-performance VLSI design
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 600–602
- Publication date
- 15 February 2026
- Language
- EN