A 3nm, 400TOPS, 1080k DMIPS SoC with Chiplet Support for ASIL D Automotive Cross-Domain Applications

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Shiro Machida, Kazuki Fukuoka, Tomoya Onda, Nobuhiro Yada, Hiroyuki Nakano, Sho Yamanaka, Hung Van Cao, Yusaku Hara, Takahiro Irita, 康平 若原, Cyril Cordoba, Tatsuya Kamei
+1 more Yasuhisa Shimazaki
DOI: 10.1109/isscc49663.2026.11409073
Cited by: 0
References: 3

Abstract

This paper presents a 3 nm SoC, designed for software defined vehicles, integrating various functions for zone-based computing. The chip includes a$1,080 \text{kDMIPS}$APU, 400TOPS NPU and$51.2 \text{GB} / \mathrm{s}$inter-chip bandwidth. Functional safety is ensured by RegionID-based FFI over UCle. Power efficiency is achieved with fine-gating across$90+$power domains with enhanced IR-drop control and ASIL D-compliant DCLS. Hierarchical mCPGs reduce clock latency. The chip supports low-power modes such as Sentry and CPD.

Fields of Study & Subjects

Embedded Systems Design Techniques Interconnection Networks and Systems Low-power high-performance VLSI design

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
168–170
Publication date
15 February 2026
Language
EN