A 28nm 47.3TFLOPs/W 894mJ/Inference Visual Autoregressive Accelerator with Differential-Amplifier Speculation and Chain-Reaction-Like Parallel Generation
Abstract
To accelerate Visual Autoregressive (VAR) applications, this work implements a 28 nm VAR accelerator achieving 47.3TFLOPs/W and$5.76 \text{mm}^{2}$chip runs at 400 MHz, accelerating DeiT/ViT VAR by$37.6 \times$with$2.75 \text{TFLOPs} / \text{mm}^{2}$area efficiency.
Fields of Study & Subjects
Advanced Neural Network Applications
Low-power high-performance VLSI design
Parallel Computing and Optimization Techniques
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 316–318
- Publication date
- 15 February 2026
- Language
- EN