A 12b 12GS/s Two-Way Interleaved Pipeline ADC with Integrated Broadband RF VGA in 5nm

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Haiyang Zhu, Larry Singer, Ron Kapusta, D.F. Kelly, Tao Pan, Mike Hensley, Scott Bardsley, Chris Dillon, Daniel Rey-Losada, Kashif M. Sheikh, Chen-Kai Hsu, Zhao Li
+9 more Janet Brunsilius, Enrique Alvarez-Fontecilla, Robert H. Bishop, Paul Wilkin, H. L'Bahy, Adalberto Cantoni, Nuo Zhang, Kaung Myat San Oo, Cihan Asci
DOI: 10.1109/isscc49663.2026.11409082
Cited by: 1
References: 11

Abstract

A 12b$12 \text{GS} / \mathrm{s}$ADC with an integrated broadband RF VGA is implemented in a 5 nm FinFET process. This combination achieves a programmable input range of 36 dB from$250 \text{mV}_{\text{ppd }}$to$16 \mathrm{V}_{\text{ppd }}$, bandwidth of 8.5 GHz, SNDR of 49 dB, SFDR of 70 dBc (with a$5.1 \text{GHz},-1 \text{dBFS}$input tone), and a single interleaving spur ($

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Advanced Power Amplifier Design Radio Frequency Integrated Circuit Design

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
202–204
Publication date
15 February 2026