Spyre: An Inference-Optimized Scalable AI Accelerator for Enterprise Workloads

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Matthew Cohen, Monodeep Kar, Swagath Venkataramani, Viji Srinivasan, B. Veraa, Matthew M. Ziegler, Nianzheng Cao, Ashish Ranjan, J. A. Silberman, Michael Guillorn, Sandra Woodward, JohnDavid Lancaster
+40 more Josh Hursey, Kyu Hyun Kim, Alberto Mannari, Amrit Nagarajan, Ananda Samajdar, Bahman Hekmatshoartabari, Bob Galbraith, Ching Zhou, Dave Satterfield, Greg Still, Gustavo Tèllez, Indira Nair, Indu Masilamanai, Jinwook Jung, Kavi Randhawa, Marcel Schaal, Martin Lutz, Paul Crumley, Philip Jacob, Prasanth Chatarasi, Radhika Jain, Saekyu Lee, Sanchari Sen, Sarada Krithivasan, Scot Rider, Shubham Jain, Siyu Koswatta, Thomas Roewer, Tom Gooding, Victor Ferrari, Vidhi Zalani, Zhibin Ren, Kevin Reick, Lisa Maurice, Chris Gonzalez, Chris Catalino, Ryan Nett, Pong-Fei Lu, Rob Senger, L.L. Chang
DOI: 10.1109/isscc49663.2026.11409090
Cited by: 2
References: 1

Abstract

Spyre is a scalable, power-efficient AI accelerator product for enterprise workloads. Featuring 32 AI cores, mixed-precision support, and LPDDR5 memory, it fits in a singleslot PCIe form factor and scales over a standard PCIE fabric. Optimized for inference workloads, Spyre achieves 2-to-3× better power/performance than GPUs on encoder-class models and scales up to 4 or more devices for large generative models.

Fields of Study & Subjects

Software System Performance and Reliability Cloud Computing and Resource Management Distributed and Parallel Computing Systems

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
52–54
Publication date
15 February 2026