8.4 A 112Gb/S/Wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS
Abstract
This work presents an 8-lane$112 ~\text{Gb} / \mathrm{s} /$wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10−14, and an energy efficiency of$1.01 \text{pJ} / \mathrm{b}$.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Low-power high-performance VLSI design
Publication details
- Journal / source
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Pages
- 140–142
- Publication date
- 15 February 2026