15.4 A 16nm 168Mb Embedded STT-MRAM with 0.0249µm 2 Bit-Cell, Dual-Port Access, and 51.2Gb/s Read Throughput for Automotive and Edge AI Applications

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Po-Hao Lee, Chia-Fu Lee, Hon-Jarn Lin, C.W. Lu, Yen-An Chang, Pranata Sanjaya, Chia-Jung Tsen, K. S. Chen, Ming Valerie Lin, C. M. Hung, Tan‐Li Chou, Chih-Hui Weng
+6 more Chia-Yu Wang, J.J. Wu, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang
DOI: 10.1109/isscc49663.2026.11409096
Cited by: 1
References: 4

Abstract

A 16nm 168Mb embedded STT-MRAM with a 0.0249μm2bit cell that overcomes density and performance challenges of competing NVM technologies is presented. The design features a modular architecture supporting customizable macros, a dual-port access scheme, and an interleaving read architecture achieving a 51.2Gb/s throughput. Fabricated in a 16nm FinFET process, the chip demonstrates a 20-year data retention at 150°C, 1M-cycle write endurance, and is suitable for automotive and edge AI applications.

Fields of Study & Subjects

Ferroelectric and Negative Capacitance Devices Neural Networks and Reservoir Computing Advanced Memory and Neural Computing

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
260–262
Publication date
15 February 2026