11.5 A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Ewout Martens, Angelo Parisi, Anirudh Kankuppe, Adam Cooman, Hanyue Li, Steven Van Winckel, Pratap Tumkur Renukaswamy, Lucas Moura Santana, Jorge Lagos Benites, Nereo Markulić, J. Craninckx
DOI: 10.1109/isscc49663.2026.11409101
Cited by: 1
References: 13

Abstract

We present a$2048 \times$time-interleaved slope-ADC implementing 7b, 175GS/s conversion. Samplers with switched buffers are proposed to realize wideband sampling in rank 1 driven by a multi-phase clock generated by a delay line with feedforward coupling. Making the slope nonlinear compensates static nonlinearities of the hierarchical sampling network. With only 0.063mm2in 5nm CMOS, it is the smallest ultra-high-speed ADC reported to date with an excellent energy per sample of less than 2.16pJ.

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Advancements in PLL and VCO Technologies Low-power high-performance VLSI design

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
198–200
Publication date
15 February 2026