21.8 A CMOS Hybrid Common-Gate Current-Integrating Sampler with >37dB SNDR Across 51GHz BW in a 128GS/s Front-End

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Jun Dai, Yi Zhong, Yunsong Tao, Aodong Zhang, Mingtao Zhan, Hao Zhang, Lu Jie, Nan Sun
DOI: 10.1109/isscc49663.2026.11409117
Cited by: 0
References: 13

Abstract

This work proposes a CMOS hybrid common-gate current integrating sampler to address linearity, BW, and jitter limitations in prior wideband ADC front-ends. The front-end employs a hybrid common-gate V-I converter, transformer-coupled inductive peaking, and an automatic power-gating hold buffer, enabling 48.1dB SFDR and 38.6dB SNDR near its 52GHz BW−3dB. This work demonstrates superior SNDRBW(measured near BW3dB), outperforming prior samplers/ADCs reported in ISSCC/JSSC/VLSI with BW>30GHz.

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Radio Frequency Integrated Circuit Design Advancements in PLL and VCO Technologies

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
378–380
Publication date
1 February 2026
Language
EN