A 1cnm 14.4Gb/s/pin 16Gb LPDDR6 SDRAM with Efficiency Mode, LDO-Based WCK Tree, Dynamic Write NT-ODT, Fast CS Control and System Meta Mode

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Jungtaek You, Mino Kim, Daehan Kwon, Sangsic Yoon, Joonhong Park, Hyungrok Do, Jeongje Park, YooSeok Jung, Seongseop Lee, Kyuyoung Kim, Hyeongsoo Jeong, Jaeyeol Kang
+20 more Hanbyeol Kwon, Minwook Oh, Jieun Kim, Jin-Seok Oh, Gi-Moon Hong, Dongyoon Ka, Seungho Lee, Heewoong Song, Minchang Kim, Daeho Yun, Sooncheol Kwon, Dongbeom Lee, Shin TaeKyun, Jongmyeong Lee, Jungmin Yoon, Kyeongpil Kang, Sanghyuk Heo, Dongkyun Kim, Jieun Jang, Hyungsoo Kim
DOI: 10.1109/isscc49663.2026.11409121
Cited by: 0

Abstract

This paper presents a 16 Gb LPDDR6 DRAM in a 1 cmm process, compliant with the JEDEC LPDDR6 specification. In implementing LPDDR6 functions, measures were taken to limit increase in power: including dynamic WR NT-ODT, LDO regulator-based WCK distribution, adding efficiency mode with power gating techniques, using fast CS control and system meta mode. These techniques enhance per-channel bandwidth by more than 50%, achieve$14.4 \text{Gb} / \mathrm{s}$at 1.025 V and improve power efficiency by over 20% compared to LPDDR5.

Fields of Study & Subjects

Low-power high-performance VLSI design Parallel Computing and Optimization Techniques Advancements in Semiconductor Devices and Circuit Design

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
266–268
Publication date
15 February 2026
Language
EN