15.9 A 48Gb/s 24Gb GDDR7 DRAM for Mid-Range Inference AI with Symmetric 2CH-Mode Operation, Clock-Path Optimization, and RAS Features

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Hyunsu Park, Sungkwon Lee, Kyunghoon Kim, Jinyoup Cha, Hyeongjun Ko, Jaehyeok Yang, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee
+15 more Jiseok Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Seulgi Kim, Eunji Song, Junghwan Ji, Byungjun Kang, Boram Kim, Sangyeon Byeon, Hankyu Chi, Hyungsoo Kim, Jonghwan Kim
DOI: 10.1109/isscc49663.2026.11409122
Cited by: 0
References: 1

Abstract

This paper introduces a GDDR7 DRAM for mid-range inference AI. A center GIO architecture is used to remove the speed penalty of the 2CH mode, which doubles memory density and reduces the clock path. This work supports ECC, CRC, and DPP to meet the RAS features required in server systems. Additionally, energy efficiency is enhanced for on-device AI applications through a low- V_DDQ mode. For nominal conditions, with a 1.2 V supply voltage, a 48 Gb/s data transmission speed is achieved.

Fields of Study & Subjects

Low-power high-performance VLSI design Parallel Computing and Optimization Techniques Advanced Memory and Neural Computing

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
270–272
Publication date
15 February 2026
Language
EN