A 0.008mm 2 16-to-1600 MHz All-Digital Fractional Divider Using AUX-DLL for Background LMS-Based DTC Calibration
Abstract
An all-digital high-performance standalone fractional divider (FDIV) is presented. It leverages a robust replica-free least-mean square (LMS)-based digital-to-time converter (DTC) background calibration using a compact auxiliary delay locked loop (AUX-DLL). The proposed FDIV provides a wide output frequency range$(16-1600 \text{MHz})$with very fine frequency resolution (50b) and achieves worst-case integrated jitter performance of$350 \text{fs}_{\text{rms}}$, while occupying only$0.008 \text{mm}^{2}$.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Analog and Mixed-Signal Circuit Design
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 174–176
- Publication date
- 15 February 2026
- Language
- EN