A 14GHz Ring-Based 3 rd -Order Fractional-N PLL with 164fs rms Jitter and a 100MHz Reference
Abstract
This work presents a 14 GHz ring-based$3^{\text{rd }}$-order fractional-N PLL with$164 \text{fs}_{\text{rms }}$jitter and a 100 MHz reference. A sub-sampling DLL is cascaded in the type-II PLL output for extra phase-noise and supply-noise suppression. A narrow-pulsed integrator is used in the sub-sampling DLL to reduce integrated jitter. A tri-state polarity-reversible SSPD is employed to reduce the DTC range and bandwidth degradation. Delay calibration is applied to reduce the VCDL delay range and implement the VCDL duty-cycle calibration.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 470–472
- Publication date
- 15 February 2026
- Language
- EN