A 2Tb 4b/Cell 6-Plane 3D-Flash Memory with 37.6Gb/mm 2 Bit Density and >85MB/s Write Throughput

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Jayanth M. Thimmaiah, Ryuji Yamashita, In-Soo Yoon, Jason Li, Cynthia Hsu, Takuya Ariki, Naoki Ookuma, Yosuke Kato, Koichiro Hayashi, Kazuki Yamauchi, K. V. Indra, Masahiro Kano
+27 more Sirisha Bhamidipati, Sneha Bhatia, Seema Malhotra, Naoki Ojima, Neil Wu, Zhiyong Yang, Frank W. Tsai, Mathias Bayle, Naoyuki Minami, Yasuyuki Fujihara, Kei Kitamura, Tomofumi Kitani, Takuyo Kodama, Takaya Handa, Naoaki Kanagawa, Yuki Ishizaki, Susumu Fujimura, Y. Suzuki, Mario Sako, Yumi Higashi, Yoshihisa Watanabe, Toshiyuki Kouchi, Aravinth V, Chin-Yi Chen, Xiang Yang, Guirong Liang, Jenny S Wang
DOI: 10.1109/isscc49663.2026.11409136
Cited by: 2
References: 1

Abstract

A 332-WL-layer stacked 2Tb 4b/Cell 6-plane 3D Flash memory achieves an areal density of$37.6 \text{Gb} / \text{mm}^{2}$. An 8 kB -physical and 16 kB -logical page architecture realizes a$85 \text{MB} / \mathrm{s}$program throughput. Write throughput is enhanced by 4.2% through voltage-level sensing based on SEN2-LBUS coupling, and an additional 8% by reduced verify operations using 4 check points. A fast SLC burst programming technique reduces program time by$\sim 11 {\%}$.

Fields of Study & Subjects

Semiconductor Lasers and Optical Devices Semiconductor materials and devices 3D IC and TSV technologies

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
254–256
Publication date
15 February 2026