15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Sunghwan Joo, Jinyeon Kim, Yongsun Lee, Ji-Young Kim, Youngsik Lee, Yongmin Kim, Chisung Oh, Kyu-Ha Shim, Haesuk Lee, Young-Yong Byun, ChangHyun Bae, Joohwan Kim
+13 more Je-Min Ryu, Shin-haeng Kang, Jaehoon Lee, Young-Uk Chang, JaeKyung Lee, Jongtae Kim Hwang, Daehwan Seo, K. Na, Y. J. SONG, Daihyun Lim, K. S. Ha, Young‐Soo Sohn, Sangjoon Hwang
DOI: 10.1109/isscc49663.2026.11409139
Cited by: 3
References: 3

Abstract

LLM-based generative AI requires high-capacity and high-bandwidth memory. We propose an HBM4 with 2048 I/Os, 3.3TB/s bandwidth, and 36GB cube density. Core die uses the 6thgen. DRAM and the base die uses a 4nm Fin-FET process. TSV count and data window are doubled for high-frequency margin. tCCDRis improved via per-channel TSV-RDQS auto calibration, enhancing rank-to-rank access. PMBIST enables at-speed testing in CoW and SiP. The on-die WDQS skew cancellation ensures robust timing, enabling reliable highspeed operation and improved yield.

Fields of Study & Subjects

Low-power high-performance VLSI design Advancements in PLL and VCO Technologies 3D IC and TSV technologies

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
264–266
Publication date
1 February 2026