8.2 A 32Gb/s 12.35Tb/s/mm 2 0.36pJ/b UCIe-Like Die-to-Die Interface Featuring Edge-Triggered Transceivers in 3nm with Active LSI Packaging

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Wei-Chih Chen, Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Wei-Shuo Lin, Yu-Jie Huang, Nai-Chen Daniel Cheng, Yu-Chi Chen, Wen-Hung Huang, Chin-Hua Wen, Hsin-Hung Kuo, Huanhuan Ke
+10 more Jie-Ren Huang, C. C. Li, Sheng-Tsung Lai, Shu-Chun Yang, Kuan-Ting Chou, Pei-Chen Chiou, Tsung-Hsien Tsai, Yi-Ting Chen, Yen‐Ming Chen, Kenny Cheng-Hsiang Hsieh
DOI: 10.1109/isscc49663.2026.11409144
Cited by: 0
References: 5

Abstract

This paper presents edge-triggered transceivers (ETT), enabling a 32Gb UCle-like chiplet interconnect when integrated within an active local silicon interconnect (aLSI). The ETT achieves power consumption of 0.07pJ/b and supports compact top-die TX/RX designs while optimizing 0.36pJ/b energy efficiency and 12.35Tb/s/mm2area bandwidth density. It demonstrates a 32Gb/s die-to-die link at 0.75V with 20.46ps eye width (65% UI) and 530mV eye height across 64 lanes in a 3nm CMOS process.

Fields of Study & Subjects

3D IC and TSV technologies Interconnection Networks and Systems Semiconductor Lasers and Optical Devices

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
136–138
Publication date
15 February 2026
Language
EN