A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving −62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mV rms DTC Supply Noise

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Damiano Fagotti, Riccardo Moleri, Michele Rossoni, Daniele Lodi Rizzini, Pietro Salvi, Stefano Gallucci, G. R. Trotta, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino
DOI: 10.1109/isscc49663.2026.11409147
Cited by: 1
References: 13

Abstract

A 28 nm fractional-N digital PLL with a supply-insensitive variable-slope digital-to-time converter (DTC) is presented. Supply insensitivity is achieved by a background calibration loop, without affecting DTC linearity or noise. Measured results demonstrate 65.6fs jitter upon 6.2 mVrms supply noise and -62dBc spurs under 10 mV pp supply-ripple over 10k-to-50 MHz disturbance frequency range. The PLL covers 8.75-to-10.25GHz tuning range, while achieving a -251 dB jitter-power figure of merit at 22.5 mW power.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Low-power high-performance VLSI design Radio Frequency Integrated Circuit Design

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
1–3
Publication date
15 February 2026
Language
EN