2.3 A 71.3mJ/Frame End-to-End Driving Processor with Flexible Heterogeneous Core Orchestration via Sparsity Reasoning
Abstract
A multi-modal end-to-end driving processor is proposed with 4 features: 1) a sparsity reasoning unit to maximize sparsity exploitation, 2) a flexible sparse-dense heterogeneous architecture with a sparsity-aware adaptive core orchestrator to maximize core utilization, 3) an energy-efficient segmented aggregation network, and 4) a long-/short-term memory unit to minimize external memory access (EMA) of temporal attention. It achieves 10.3fps at 71.3 mJ/frame, consuming 218× less energy than a state-of-the-art driving SoC.
Fields of Study & Subjects
Advanced Neural Network Applications
Embedded Systems Design Techniques
Parallel Computing and Optimization Techniques
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 46–48
- Publication date
- 15 February 2026
- Language
- EN