A 77GHz 8-bit CMOS Phase Shifter Adopting a Nested-Vector-Based Error Correction with 0.33°/0.07dB RMS-Error for MIMO Radar Applications
Abstract
In this paper, we present a 77GHz 8-bit nested vector-sum phase shifter in 28nm CMOS. The architecture performs vector modulation by splitting a single outer vector into two inner vectors generated by a two-stage I/Q coupler. Owing to its insensitivity to I/Q mismatch and the peak error smoothing technique, the phase shifter achieves 0.33° and 0.065dB rms phase and gain errors while occupying a core area of 0.17mm2.
Fields of Study & Subjects
Radio Frequency Integrated Circuit Design
Advancements in PLL and VCO Technologies
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 480–485
- Publication date
- 1 February 2026
- Language
- EN