A 1.2GHz 12.77GB/s/mm 2 3D Two-DRAM-One-Logic Process-Near-Memory Chip for Edge LLM Applications

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Y. Charles Cao, Jinghao Jiang, Haijun Jiang, Qian Zhang, Xuanzhi Liu, Jinhui Cheng, Zhongze Han, Xiping Jiang, Fengguo Zuo, Song Wang, Fujun Bai, Yixin Guo
+5 more Chunmeng Dou, Jianguo Yang, Hangbing Lv, Qi Liu, Ming Liu
DOI: 10.1109/isscc49663.2026.11409184
Cited by: 2
References: 3

Abstract

A high-bandwidth-density$(12.77 \text{GB} / \mathrm{s} / \text{mm}^{2})$high-memory-density$(99.4 \text{Mb} / \text{mm}^{2})$low-energy-consumption$(0.67 \text{pJ} / \mathrm{b})$3D PNM design that operates at 1.2 GHz is presented. The design adopts a two-DRAM-one-logic architecture that enables near-DRAM computing through a high-density 3D integration path, reducing memory-access latency by up to 93% and GEMM execution time by up to 98%, demonstrating strong potential for edge-LLM workloads.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies 3D IC and TSV technologies Radio Frequency Integrated Circuit Design

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
524–526
Publication date
15 February 2026