7.8 A 55nm Intelligent Vision SoC Achieving 346TOPS/W System Efficiency via Fully Analog Sensing-to-Inference Pipeline

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Zhengke Yang, Haofeng Yu, Xia Liu, Zhen Kong, Humiao Li, Liang Ran, Zhichao Lyu, Xinhe Feng, Liang Zhao, Yida Li, Jiamin Li, Feichi Zhou
+1 more Longyang Lin
DOI: 10.1109/isscc49663.2026.11409209
Cited by: 1
References: 13

Abstract

This work presents a fully analog intelligent vision SoC that eliminates both sensorprocessor and inter-layer A/D conversions for end-to-end vision. A continuous analog datapath from sensing to multi-layer inference is enabled by a PWM imager, an RRAM-based CIM, and a linearity-recovery analog memory. Fabricated in 55 nm CMOS, the chip achieves 11pJ/(pixel.frame) sensing efficiency, 8,791 TOPS/W MAC efficiency, and 346 TOPS/W system-level efficiency across diverse vision tasks.

Fields of Study & Subjects

CCD and CMOS Imaging Sensors Analog and Mixed-Signal Circuit Design Advanced Memory and Neural Computing

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
126–128
Publication date
15 February 2026