31.1 A 14.08-to-135.69Token/s ReRAM-on-Logic Stacked Outlier-Free Large-Language-Model Accelerator with Block-Clustered Weight-Compression and Adaptive Parallel-Speculative-Decoding

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026 Open access

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Authors: Pingcheng Dong, Yonghao Tan, Xuejiao Liu, Peng Luo, Yu Liu, Di Pang, Songchen Ma, Xijie Huang, Shih-Yang Liu, D. Zhang, Zhichao Lu, Luhong Liang
+4 more Chi-Ying Tsui, Fengbin Tu, Liang Zhao, Kwang-Ting Cheng
DOI: 10.1109/isscc49663.2026.11409211
Cited by: 1
References: 6

Abstract

This work presents a 55nm speculative decoding-based LLM accelerator with bumpingbased face-to-face ReRAM-on-logic stacking technology. It features a local rotation unit for outlier-free low-bit quantization, a stacking-aware PNM architecture co-designed with blockwise vector quantization to reduce weight EMA overheads, and an adaptive parallel speculative decoding scheme with out-of-order scheduler for high resource and bandwidth utilization. Our chip achieves 14.08-to-135.69token/s and 4.46-to-7.17× speedup over vanilla speculative decoding.

Fields of Study & Subjects

Parallel Computing and Optimization Techniques Speech Recognition and Synthesis Embedded Systems Design Techniques

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
532–534
Publication date
15 February 2026
Language
EN