33.6 A Frequency-Translated, 1-to-5GHz Centred, All-Passive, Programmable-Bandwidth, Switched-Capacitor Delay Line with 6.5-to-8.2dB Delay-Independent Insertion Loss in 65nm CMOS
Abstract
We propose an all-passive, programmable-bandwidth, frequency-translated switched- NF+5.5dBm. In a narrow-bandwidth mode the DL has the OOB-IIP3 of capacitor delay line (DL) with a 6.5-to-8.2dB delay-independent insertion loss in 65nm +28dBm. The DL consumes an average power between 12 and 33mW across all bandwidth CMOS. The DL offers tunable bandwidth (0.2 to 1 GHz) and tunable centre frequency (1 to settings. 5GHz) while supporting ns delay range. The results demonstrate a$\text{delay-range} \times$BW of 3,
Fields of Study & Subjects
Radio Frequency Integrated Circuit Design
Analog and Mixed-Signal Circuit Design
Advancements in PLL and VCO Technologies
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 1–3
- Publication date
- 15 February 2026
- Language
- EN