37.7 A 12.8Gb/s Parallel Receiver with a One-Way Self-Training Scheme for Equalizing ISI and Reflections in Multi-Drop Memory Interfaces

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

View at publisher
Authors: J . K . Moon, Taehyeon Kim, Minwook Kim, Hyeonwoo Seong, Jewon Lee, Jeongbin Park, Dongjun Park, Jaehoon Lee, Jung-June Park, Chi-Weon Yoon, Jae‐Yoon Sim, Seon‐Kyoo Lee
DOI: 10.1109/isscc49663.2026.11409228
Cited by: 0
References: 2

Abstract

This paper presents a$12.8 \text{Gb} / \mathrm{s} /$pin receiver with a one-way self-training scheme for highly-reflective multi-drop memory interfaces. DFE tap coefficients are directly derived from a single-pulse response, eliminating controller interaction during training. Implemented in 40 nm CMOS, the receiver reopens a closed eye in a 4-drop channel at BER$

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Low-power high-performance VLSI design Analog and Mixed-Signal Circuit Design

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
636–638
Publication date
15 February 2026
Language
EN