A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing
Abstract
We present a silicon-verified fully digital SRAM-CIM macro that supports multi-bit hybrid SNN-CNN processing. Key innovations include: (1) a compact CFD-SC-RC architecture that shares SNN-CNN MAC hardware to minimize area and energy overhead while enabling adaptive model and precision selection; and (2) a PS-WR-ODM scheme that balances partial-sum storage and weight-update energy. Fabricated in 16nm FinFET CMOS, the test chip achieves 444.21TOPS/W (1 bIN-8bW-14bOUT, SNN) and 62.84TOPS/W(8bIN-8bW-22bOUT, CNN).
Fields of Study & Subjects
Low-power high-performance VLSI design
Advanced Memory and Neural Computing
Parallel Computing and Optimization Techniques
Publication details
- Journal / source
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Pages
- 526–528
- Publication date
- 15 February 2026