32.3 An 85.1dB-SNDR 8MS/s Incremental Pipeline ADC with Dual-Residue-Assisted Exponential Quantization
Abstract
This paper presents an incremental pipeline ADC with dual-residue architecture. An exponential$\Delta \Sigma$loop is proposed to directly quantize the residue, replacing conventional interpolators that are complex and less accurate. It enables fast and high-precision backend conversion while maintaining insensitivity to inter-stage gain variations. The prototype achieves 85.1 dB SNDR, the highest among comparable dual-residue ADCs, and 8MS/s conversion speed, the fastest among comparable high-precision incremental ADCs.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Advanced Memory and Neural Computing
Low-power high-performance VLSI design
Publication details
- Journal / source
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Pages
- 556–558
- Publication date
- 15 February 2026