A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces
Abstract
This paper presents a 72Gb/s/pin PAM-3 single-ended transceiver in 28nm CMOS. Driver-cooperative coding enhances signal integrity and reduces signaling power by$\geq 46 \%$. Asymmetric data-dependent equalization and bias peaking mitigate PAM-3 different edge ISI and switching jitter, enlarging eye area by$1.9 \times$and$2.8 {\times}. \mathrm{A} \frac{1}{8}$-rate forwarded-clock multiplication scheme enables low-power and wide-range de-skew. The transceiver supports a 72Gb/s/pin data rate, with power efficiencies of 0.7pJ/b at 48Gb/s and 1.17pJ/b at 72Gb/s.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Low-power high-performance VLSI design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 624–626
- Publication date
- 15 February 2026
- Language
- EN