2.5 A 1.1mm 2 , 14.4ns, 13.1pJ/b Forward Error Correction with Ordered-Statistics Post Processing for Ultra-Reliable and Low-Latency Communications
Abstract
We present a two-stage FEC decoder that combines soft-decision Chase decoding with order-1 ordered statistics decoding, offering robust error correction for URLLC. A 1.1 mm2, 16 nm decoder prototype with optimized Gaussian elimination and early exits achieves an average latency of 14.4 ns and a worst-case latency of 132.6 ns, improving upon prior work by$53 \times$and five orders of magnitude, respectively. The prototype delivers 15.2 Gbps at 13.1 pJ/b, outperforming state-of-the-art URLLC FEC decoders.
Fields of Study & Subjects
Error Correcting Code Techniques
Coding theory and cryptography
Low-power high-performance VLSI design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 50–52
- Publication date
- 15 February 2026
- Language
- EN