A 103.9dB-SFDR 83.8dB-SNDR 3MHz-BW Multi-Bit Quadratic-Exponential Noise-Coupled IDSM with High Tolerance to DAC Non-Linearity
Abstract
This paper presents a quadratic-exponential noise-coupled (NC) IDSM to achieve a quantization noise shaping effect greater than$4^{\text{th }}$order with OSR 22, while having high tolerance to DAC non-linearity and a small noise penalty factor. The DAC2 and adder in NC are reused for a larger effective OSR and improve energy efficiency. Implemented in 28nm CMOS, the IDSM achieves an SNDR/SFDR of$83.8 \text{dB} / 103.9 \text{dB}$, with a 3 MHz bandwidth, and$794 \mu \mathrm{W}$, resulting in Schreier FoM$\mathrm{M}_{\text{SNDR }} / \text{FoM}_{\text{DR }}$of$179.6 \text{dB} / 181.4 \text{dB}$.
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 558–560
- Publication date
- 15 February 2026
- Language
- EN