11.1 A 14b 400MS/s TDC-Assisted Pipelined-SAR ADC with Rail-to-Rail Input VTC and Background Time-Domain Error Calibration

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Jingpeng Wang, Bingrui Li, Haoyang Luo, Mingtao Zhan, Xiyu He, Dawei Shen, Lu Jie, Xiyuan Tang
DOI: 10.1109/isscc49663.2026.11409270
Cited by: 0
References: 21

Abstract

This paper presents a 14b 400MS/s Pipelined-SAR ADC utilizing a front-end TDC with a linearized rail-to-rail input VTC. A background calibration engine corrects VTC gain and time-domain offset errors by monitoring digital output statistics with minimal analog overhead. A replica-biasing-based ring amplifier improves energy efficiency and robustness. The 28nm chip achieves 67dB Nyquist SNDR at 4.6mW with a 6.3fJ/conv-step FoMw and 173.5dB FoMs.

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Advancements in PLL and VCO Technologies Radio Frequency Integrated Circuit Design

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
190–192
Publication date
15 February 2026
Language
EN