A 12nm 4Mb 104.56-to-137.75TFLOPS/W Charge-Trap Transistor-Based Computing-in-Memory Macro Using Analog-Predict-Digital-Compute for AI Edge Devices

2026 IEEE International Solid-State Circuits Conference (ISSCC) 2026

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Authors: Junzhe Shen, Zhidao Zhou, Wenfeng Zha, Z. Li, Weizeng Li, Bohan Wang, Junyu Zhu, Hanghang Gao, Zhongze Han, Y. F. Wang, Linfang Wang, Hongyang Hu
+3 more Qing Luo, Chunmeng Dou, Ming Liu
DOI: 10.1109/isscc49663.2026.11409272
Cited by: 2
References: 17

Abstract

Previous non-volatile CIM (nvCIM) macros suffer from low storage density, unnecessary multiply-and-accumulate (MAC) operations, and large hardware cost for floating point computations. A 4Mb CTT nvCIM macro, fabricated in 12nm CMOS, supports INT/FP4 MAC operations with the analog-predict-digital-compute scheme for power saving, achieving an energy-efficiency of 137.75TFLOPS/W and >40 times improved density FoM (storage density×computing density).

Fields of Study & Subjects

Ferroelectric and Negative Capacitance Devices Advanced Memory and Neural Computing Advancements in Semiconductor Devices and Circuit Design

Publication details

Journal / source
2026 IEEE International Solid-State Circuits Conference (ISSCC)
Publisher
IEEE
Pages
514–516
Publication date
15 February 2026