A 0.23pJ/b 24Gb/s Modular D2D Interface with Zero Wake Penalty Clock Gating in 3nm

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Ravi Shivnaraine, Charles. Boecker, Eric Groen, S. Z. Li, Ping Lu, Socrates D. Vamvakos, Roxanne Vu, Chris Hanke, Shankar Tangirala, Wen Liu, Marina Salik, Kevin Bartholomew
+7 more Sushmitha Reddy, Alex Tessitore, Aws Shallal, Kalyan Nallaparaju, Jin Liang, Minhan Chen, Shaishav Desai
DOI: 10.1109/isscc49663.2026.11409276
Cited by: 0
References: 5

Abstract

This work presents a$3 ~\text{nm} 24 ~\text{Gb} / \mathrm{s}$D2D Interface achieving$0.23 \text{pJ} / \mathrm{b}$(analog PHY power) and zero wake penalty clock gating and$0.17 \text{pJ} / \mathrm{b}$at$20 ~\text{Gb} / \mathrm{s}$. The PHY achieves a total end-to-end average latency of 4.2 ns ($\sim 25 \%$analog macro). Measured performance demonstrates a worst-case bit-error rate, extrapolated to 1e-18 measured across 1680 lanes over PVT of$12 \text{ps}_{\text{pp}}$. The modular nature of this work allows flexibility in the construction of D2D links and natively supports asymmetric TX and RX bandwidths.

Fields of Study & Subjects

Interconnection Networks and Systems Low-power high-performance VLSI design 3D IC and TSV technologies

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
138–140
Publication date
15 February 2026
Language
EN