MADiC: A 3nm 7.4TOPS/mm 2 , 17.4TOPS/W Generative Diffusion Accelerator Enabled by Hardware-Compiler Co-Optimization of Memory Hierarchy and Operator Parallelism

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Shih-Wei Hsieh, Yi-Syuan Chen, Ping-Yuan Tsai, M. Lin, Chia-Yuan Cheng, Lien-Feng Hsu, Po-Hao Huang, Hung-Wei Chih, Po-Han Chiang, Chia-Ming Chang, Ming-Hsuan Chiang, Chia-Hung Yuan
+15 more Sheng-Po Kuo, Viswanath Uggu, Chun-Kun Chan, Ming-En Shih, Yu-Cheng Tseng, Hsin-Ping Cheng, Stan Huang, Chia-Ping Chen, ShenKai Chang, Chih-Ming Wang, Po-Yu Yeh, J. G. Liu, Yung-Chang Chang, Chi-Cheng Ju, Yucheun Kevin Jou
DOI: 10.1109/isscc49663.2026.11409294
Cited by: 0
References: 14

Abstract

This work presents MADiC, a 3nm 0.338mm2diffusion accelerator for generative image editing on edge devices. MADiC features design-time L1/L2 memory optimization, cross-loop feature map allocation with write-over-read relaxation, and activation-aware input preloading with concurrent resizing. Operating at 0.575V and 546MHz, it delivers 7.4TOPS/mm2and 17.4TOPS/W when running the Diffusion ConvNet model.

Fields of Study & Subjects

Advanced Neural Network Applications Parallel Computing and Optimization Techniques Low-power high-performance VLSI design

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
1–3
Publication date
15 February 2026
Language
EN