A 28nm CMOS SAR-Based Continuous-Time Pipeline ADC with 103dB SFDR and 270MHz Bandwidth Using NCF and DAC Error Calibration

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Qilong Liu, Robert Rutten, Muhammed Bolatkale, Arda Aralioglu, Gilbert Hardeman, Emil Siby, Patrick van Mourik, Vinoth Ilamurugan, Shagun Bajoria, Lucien J. Breems
DOI: 10.1109/isscc49663.2026.11409299
Cited by: 0
References: 11

Abstract

This 28nm CMOS SAR-based continuous-time pipeline ADC for automotive receivers achieves −95dBc THD and 103dB SFDR in 270MHz bandwidth, exceeding state-of-the-art by >20dB. Wideband high spectral purity is realized with a highly linear all-pass filter, high-SFDR coarse ADCs, a fast tone-based frequency-domain noise-cancellation filter calibration and a correlation-based element-wise DAC gain and timing error calibration. Power and area, including LDOs and calibrated filters is 155mW and 1.4mm2.

Fields of Study & Subjects

Analog and Mixed-Signal Circuit Design Radio Frequency Integrated Circuit Design Advancements in PLL and VCO Technologies

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
192–194
Publication date
15 February 2026
Language
EN