A Fully Integrated Piezoelectric Energy-Harvesting Interface with Single-Stage Bias-Flip and MPPT Achieving $\mathbf{5. 6 3} \boldsymbol{\times}$ Maximum Output Power Improving Rate
Abstract
This paper presents a fully integrated PEH interface that enhances output power while minimizing on-chip capacitor area. The proposed design employs a SC structure that reuses both the piezoelectric capacitor and the rectifier capacitor as flying capacitors. Meanwhile, on-chip capacitors serve as DC capacitors, thereby eliminating parasitic-capacitance losses. As a result, the interface achieves a maximum output power improvement of$5.63 \times$and a normalized on-chip capacitor area of$0.09 \text{mm}^{2} / \text{nF}$.
Fields of Study & Subjects
Innovative Energy Harvesting Technologies
Analog and Mixed-Signal Circuit Design
Advanced DC-DC Converters
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 280–282
- Publication date
- 15 February 2026
- Language
- EN