37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Yoonjae Choi, Daero Kim, M.G. Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Min Cho, Boyoung Kang, Kyoungwon Lee, Jaegeun Song
+5 more Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew
DOI: 10.1109/isscc49663.2026.11409321
Cited by: 0
References: 1

Abstract

This paper presents a 2 nm all-digital LPDDR6 PHY that achieves 14.4 Gb/s/pin, increasing bandwidth while optimizing power. Key innovations include quadrature clocking, with QEC, to reduce jitter sensitivity, and a multi-level FIFO-based speculative DFE to relax timing constraints in standard-cell implementation. An efficiency mode, employing clock gating, dramatically reduces power. A reconfigurable serializer supports both 1:6 and 1:8 DFIs, ensuring high bus efficiency and backward compatibility.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Low-power high-performance VLSI design Embedded Systems and FPGA Applications

Publication details

Journal / source
Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages
628–630
Publication date
15 February 2026
Language
EN