8.9 A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces
Abstract
This paper presents a 72Gb/s/pin single-ended simultaneously bi-directional (SBD) TRX in 28nm CMOS. Capacitive peaking leakage cancellation (CPLC) suppresses the high-frequency leakage due to the main and hybrid driver mismatch in SBD links by 63%. Dual-loop hybrid impedance calibration reduces the coefficient errors of the hybrid circuits under PVT variations by 92%. The TRX achieves a 72Gb/s data rate with an eye-opening of 0.45UI and 243mV and an energy efficiency of 1.5pJ/b.
Fields of Study & Subjects
Advancements in PLL and VCO Technologies
Radio Frequency Integrated Circuit Design
Microwave and Dielectric Measurement Techniques
Publication details
- Journal / source
- 2026 IEEE International Solid-State Circuits Conference (ISSCC)
- Publisher
- IEEE
- Pages
- 150–152
- Publication date
- 15 February 2026