15.2 A 350mV Single-Rail SRAM Using a Custom-Logic-Bitcell in 2nm-CMOS-Nanosheet Technology for Mobile and Edge-AI Applications
Abstract
This work presents a single-rail,$21.04 \text{Mb} / \text{mm}^{2}$logic-bitcell 2-port SRAM in a 2 nm nanosheet technology for CPU, GPU and NPU caches. The implemented ×BIT cell in a$2 \mathrm{R} \times 1 \mathrm{C}$configuration uses dual BL for balanced NMOS/PMOS devices to form a rectangular array and maximize area density. Optimized for dynamic power, it operates reliably from$0.35-1.2 \mathrm{V}$, achieving an industry-leading 102ps read-access time to support 4 GHz processor and making it ideal for shallow-depth caches.
Fields of Study & Subjects
Low-power high-performance VLSI design
Advancements in Semiconductor Devices and Circuit Design
Advanced Memory and Neural Computing
Publication details
- Journal / source
- Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
- Pages
- 256–258
- Publication date
- 15 February 2026
- Language
- EN