A −66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC

Pietro Salvi; Michele Rossoni; Riccardo Moleri; Daniele Lodi Rizzini; Damiano Fagotti; Stefano Gallucci; Andrea Leonardo Lacaita; Simone Mattia Dartizio; Salvatore Levantino

doi:10.1109/isscc49663.2026.11409352

A −66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference 2026

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Authors: Pietro Salvi, Michele Rossoni, Riccardo Moleri, Daniele Lodi Rizzini, Damiano Fagotti, Stefano Gallucci, Andrea Leonardo Lacaita, Simone Mattia Dartizio, Salvatore Levantino

DOI: 10.1109/isscc49663.2026.11409352

Cited by: 0

References: 12

Abstract

A fractional-N digital PLL adopting a pseudo-differential inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive blocks. The PLL achieves integrated jitter below 59fs under 10mVpp sinusoidal disturbance applied to the DTC supply in the fractional-N mode, with fractional spurs below −66dBc and the jitter-vs-power figure of merit of −251.4dB.

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Analog and Mixed-Signal Circuit Design Radio Frequency Integrated Circuit Design

Publication details

Journal / source: Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Pages: 212–214
Publication date: 15 February 2026
Language: EN

References 12