Global Stress Analysis in Fin-Patterned Si/SiGe Nanosheets Stack and Its Impact on GAA-NS Transistors for Next-Generation CMOS Technology

Si/SiGe nanosheet (NS)-based CMOS technology is emerging as a leading candidate for sub-3 nm technology nodes owing to its excellent electrostatic control and scalability. A critical challenge, however, lies in understanding the stress evolution during sequential stacking and fin patterning of Si/SiGe nanosheets, which strongly impacts carrier transport and reliability of the IC. In this work, we systematically investigate the stress distribution in Si/SiGe superlattice nanosheets after fin pattering and analyze its influence on the Si channel region of gate-all-around nanosheet (GAA-NS) transistors. The SiGe nanosheets (Ge mole fraction = 0.35) exhibit an initial compressive stress of 2.17 GPa, while the Si nanosheets are initially stress-neutral. Fin patterning induces tensile stress in the Si layers due to relaxation of compressive stress in the SiGe nanosheets, leading to a residual tensile stress in the final GAA-NS channel. The extracted maximum in-plane stresses reach 0.43 GPa (σxx, along the channel length) and 0.96 GPa (σyy, along the width), depending on device geometry. Electrical simulations confirm that this residual biaxial tensile stress enhances the drive current of both n-type and p-type GAA-NS transistors by more than 8 % at a fixed gate metal work function. These findings offer crucial design insights for stress-engineered Si/SiGe nanosheet CMOS technology to boost device performance and ensure reliability at beyond-3 nm nodes.