Low-Power Stack-Level Programming Enabled by Optimized Dummy Word Line Voltage in 3-D NAND Flash Memory

In this paper, we propose a low-power stack-level programming scheme for ultrahigh stack 3D NAND flash memory. As the number of word lines (WLs) increases beyond 300 layers, the increased pass voltage leads to excessive power consumption and reliability degradation such as pass disturbance. To address this, we investigate various pass biasing techniques using dummy word lines (DWLs) in a triple-stack structure using TCAD simulation. The proposed bottom stack program method (Case 1-c) ensures sufficient channel potential in the inhibit string and minimizes the hot carrier injection (HCI) problem. Furthermore, the proposed middle stack program method (Case2-d) deliberately relocates band-to-band tunneling (BTBT) regions near the DWLs to mitigate HCI near the selected word line. The proposed techniques effectively reduce the power and cell stress in high-stack 3D NAND architectures, while ensuring sufficient channel potential for reliable program operation.