Experimental Verification and Analytical Modeling of the Zero Temperature Coefficient in Half-Diamond and Diamond MOSFETs Under High-Temperature

This work presents an analytical and experimental investigation of the Zero Temperature Coefficient (ZTC) behavior for the drain current (IDS) in Half-Diamond (HDM) and Diamond (DM) Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (MOSFETs) across Triode and Saturation regions under high-temperature (T) conditions. The accuracy of the Camillo-Martino model (CM-Model) in predicting the gate voltage (VGS) at this bias point (VZTC) was evaluated using 180 nm Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology. Results confirm that HDM and DM preserve the Longitudinal Corner Effect (LCE) and the Parallel Connections of MOSFETs with Different Channel Lengths Effect (PAMDLE) under high-T, yielding higher IDS/(W/L) than equivalent rectangular (RM) MOSFETs. The HDM exhibited IDS/(W/L) gains at ZTC of 50.3% and 71.6% (Triode and Saturation) over RM, while DM showed gains of 44.3% and 52.9%, respectively. Similar VZTC values across all devices (3.2% maximum difference) confirm that innovative gate geometries do not alter ZTC biasing. Overall, HDM provides superior thermal stability, higher IDS capability, and reduced die area for low-power, high-T CMOS ICs. The CM-Model strongly agreed with experimental data, validating its use for innovative gate layouts with maximum errors of 0.79% (Saturation region) and 5.72% (Triode region) above 325 K.