Grid-Side Effect Mitigation of High Speed Sensorless Control in PMSM Drives Fed by Film DC-Link Capacitor and Single-Phase Diode Rectifier

Electrolytic capacitor-less permanent magnet synchronous motor (PMSM) drives have gained significant attention in both academic and industrial sectors due to their advantages in cost, integration, and reliability. However, the fluctuating DC-link voltage can transfer grid-side harmonics to the back electromagnetic force (BEMF), resulting in inaccurate position estimation at medium to high speeds. To address this issue, a novel and straightforward method is proposed, which integrates the multiple delayed signal cancellation (MDSC) technique into a Type-II phase-locked loop (PLL) to suppress both the fundamental and higher-order harmonics. Additionally, the use of an in-loop filtered PLL structure simplifies the design, requiring only one scalar filter and two delayed operators, which makes it less complex than existing strategies. A harmonic content analysis is also conducted to elucidate the harmonic orders and their detrimental effects on position estimation. Finally, the proposed approach is validated through experiments on a real hardware test bench, demonstrating its effectiveness and advantages.