Optimization of Current Balance for Multichip Parallel SiC Power Modules Based on Response Surface Methodology and Genetic Algorithm

Due to the limited current handling capability of individual SiC MOSFETs, multichip parallel configurations are essential for high-power applications. However, such configurations inherently suffer from current imbalance, leading to uneven power losses and undesired oscillation, which accelerate fatigue and raise reliability concerns. This paper presents a method to achieve balanced current distribution in multichip parallel SiC power modules by optimizing bonding wire configurations. Firstly, the current sharing mechanisms in the dynamic and static stages are analyzed. Subsequently, response surface methodology is applied to establish the functional relationship between bonding wire landing points and power source inductances, enabling rapid evaluation during the optimization process. A multi-objective genetic algorithm (NSGA-II) is then employed to balance and minimize parasitic inductances simultaneously. To address the source potential imbalance caused by the discrepancies between commutation loop and output loop, power balance bonding wires are introduced. Finally, experimental verification using double pulse tests demonstrates that the optimized structure reduces the dynamic MCI (maximum current imbalance) of 17.5% and static MCI of 6.2% to values below 4%.