Investigation of Degradation Mechanism in 1200-V SiC MOSFETs Under Surge Current Stress of Body Diode Using Electrothermal–Mechanical Analysis

Surge reliability of SiC MOSFETs is critical for power electronic systems，mainly focusing on electro-thermal analysis. The impact of electro-thermal-mechanical influence is rarely detailed explained. This study systematically analyzed the failure mechanisms of 1200 V SiC Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) of both asymmetric trench and planar gate under surge current stress, using both experimental and numerical TCAD simulations. The impact of thermo-mechanical stresses on both the package and the chip performance was compared. The study revealed that the package of two devices exhibited distinct behaviors under surge current stress: for the asymmetric trench SiC MOSFET, no cracks were observed between the epoxy resin and the metal layer; whereas for the planar gate SiC MOSFET, cracks formed between the epoxy resin and the metal layer. This difference is primarily due to the thermomechanical stress variations between the epoxy resin and the metal layer in the two devices. At the chip level, both devices shared a common failure mode, where the high temperatures generated during the surge process amplify the effects of thermal expansion coefficient mismatches between different materials. This results in compressive stress within the interlayer dielectric due to the thermal expansion coefficients mismatch between the source aluminum and the interlayer dielectric, ultimately causing dielectric rupture and subsequent aluminum-gate shorting that leads to device failure. This failure mechanism further reveals the vulnerability of SiC MOSFETs under extreme operating conditions.